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order this data sheet from logic marketing semiconductor technical data ? motorola, inc. 1995 4/95 rev 1.3

overview the fddi is a lan standard under ansi auspices. the standard supports a 100 mbps fiberopticbased token ring with up to 1000 stations; total ring length should not exceed 200 km with up to 2 km between stations. fddi over twistedpair cable is also supported by the tppmd standard. the twisted pair cable connecting two stations can be up to 100 meters in length. users are encouraged to refer to the pertinent ansi standard documents for further information. introduction the MC68835 t wistedpair interface chip (tpic) is a transceiver capable of transmitting and receiving ml t3 or nrzi encoded data streams, as well as handling clock and data recovery . the tpic implements the lower portion of the physical layer (phy) functions of the fddi standard. it performs a fivebit parallel to serial conversion during transmission, as well as a fivebit serial to parallel conversion during reception. the tpic uses the fivebit parallel interface to communicate with the mc68837 elastic buf fer and link manager (elm) device or other motorola fddi devices that incorporate the elm function internally , such as the 68840 ifddi, 68848 camel, or the 68847 quad elm. MC68835 features ? supports twisted pair and fiber optic media ? supports mlt3 line code in twisted pair mode ? supports nrzi line code in fiber mode ? adaptive receive equalization supports tp line lengths of 0 to 100 meters ? controlled twisted pair output transition times may eliminate need for transmit filter ? tp receiver includes circuitry which enables error free reception of data distorted with base line wander ? twisted pair and fiber transmitters share same ic pins. twisted pair and fiber receivers also share same ic pins ? twisted pair or fiber optic operation selected with portsel input ? twisted pair (tp) transceiver complies with ansi x3t9.5 tppmd fddi standard ? meets jitter requirements of ansi x3t9.5 tppmd ? pseudoecl interface for fiberoptic media ? digital phaselocked loop (dpll) provides run length immunity ? transmit off capability for true quiet line state ? uses a 25 mhz external frequency reference ? converts received serial bit stream to fivebit parallel form ? recovers 125 mhz clock from incoming serial nrzi or mlt3 data stream ? generates 25 mhz receive clock ? small number of passive external components required ? selectable low power mode ? loop back capability ? single +5v power supply ? utilizes 0.8um bicmos technology ? 10mm x 10mm, 64 pin, tqfp package this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. fa suffix tqfp package case 93102
MC68835 2 motorola timing solutions br1333 e rev 4 functional description figure 1. simplified block diagram for twisted pair applications of the MC68835 tpic sd figure 2. simplified block diagram for optical fiber applications of the MC68835 tpic elm rsclk rdatax tdatax MC68835 rdl rdh tdl tdh transformers rdl rdh tdl tdh tp connector sd elm rsclk rdatax tdatax MC68835 rdl rdh tdl tdh fiber interface components rdl rdh tdl tdh fiber connector sdl sdh sdl sdh
MC68835 3 motorola timing solutions br1333 e rev 4 tp input figure 3. MC68835 simplified block diagram elm logic rsclk rdata [4:0] sd fo lb tdata [4:0] serial to parallel conversion nrzi to nrz decoder dpll receiver mlt3 to nrzi auto equalization squelch rdh/l elm interface media interface tp output parallel to serial conversion nrz to nrzi encoder transmitter nrzi to mlt3 wave shaping driver tdh/l tptslrt tclkin freq mult awake system mgt fiber (pecl) input portsel sdh/l fiber (pecl) input
MC68835 4 motorola timing solutions br1333 e rev 4 pin assignments figure 4. MC68835 pinout: 64lead tqfp package (top view) gnd gnd rdata0 rdata1 rdata2 rdata3 rdata4 rsclk tdata4 tdata3 tdata2 tdata1 tdata0 gnd gnd mclkin vddfin sdh sdl gndfin vddtpr tprecb rdh rdl c2 c1 gndtpr gnd gnd gnd gndio tclkin vddfm nc gndfm sd gnd gnddig ts vddclk bytclk symclk gndclk gnd gnd gnd gnd vddio portsel awake vdddig gndbg rreftpt gndtpt vddtpt tdl tdh tptslrt vddfout gndfout gnd 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 MC68835 nc fo lb
MC68835 5 motorola timing solutions br1333 e rev 4 table 1. media interface pins pin no. pin name pin type pin description 11 12 tdl tdh o differential transmitter outputs these pins are shared by two types of transmitters. when por tsel is in the high logic state the twisted pair t ransmitter is enabled. when low the fiber t ransmitter is enabled twisted pair mode: in twisted pair mode mlt3 coding is used. ml t3 data contains three logic states: +1, 0, and 1. the +1 logic state is produced when the tdh output is activated while the tdl output is of f. the 1 logic state is produced when the tdl output is activated while the tdh output is of f. the 0 logic state is produced when both outputs are active. fiber mode: in fiber mode the transmit data stream is nrzi encoded. a positive dif ferential output voltage represents that light energy is to be transmitted on the fiber media, and a negative dif ferential output voltage represents that no light energy is to be transmitted on the fiber media. the signal changes at a 125 mbps rate. 22 23 rdl rdh i differential receiver inputs these pins are shared by two types of receivers. when por tsel is in the high logic state the t wisted pair receiver is enabled. when low , the fiber receiver is enabled twisted pair mode: the inputs are connected to a receiver which features adaptive equalization and squelch capabilities. the squelch capability blocks signals which do not meet a preset minimum level specification. fiber mode: a positive dif ferential voltage applied to these inputs represents active light energy on the fiber media, and a negative dif ferential voltage represents no active light energy on the fiber media. the signal changes at a 125 mbps rate. 28 29 sdl sdh i pecl fiber signal detect differential receiver inputs a positive dif ferential voltage applied to these inputs represents an active fiber link and a negative dif ferential voltage represents an inactive fiber link. this input changes infre - quently. table 2. mode select pins pin no. pin name pin type pin description 4 portsel i ttl port select when high, the por tsel input causes the twisted pair port and ml t3 coding to be selected. when low , it causes the fiber port and nrzi coding to be selected. the power consumption is minimized in the circuitry associated with the unselected port. 5 awake i ttl awake input when the aw ake input is set to the high logic state, the MC68835 operates in its normal mode. in the normal mode, only the active port (twistedpair or fiberoptic) is pow - eredup. to conserve power , the unused port is powereddown. when neither port is being used, the aw ake input may be driven to the low logic state where the MC68835 operates in a low power asnoozeo mode. in this low power mode the system clocks con - tinue to operate. 13 tptslrt i ttl twisted pair transmitter slew rate select when the tptslr t input is set to the high logic state, the output slew rate will be at about 2.5ns/volt. when the tptslr t is set to the low logic state, the slew rate will be at about 4ns/volt. 1 in the low slew rate mode, it may be unnecessary to utilize an external transmit filter. 39 ts i ttl three state enable when low, this input causes all the rdat a outputs and the rsclk and sd outputs to go to the high impedance state. 1. specification established by design and laboratory characterization
MC68835 6 motorola timing solutions br1333 e rev 4 table 3. elasticity link manager (elm) interface pins pin no. pin name pin type pin description 42 sd o ttl signal detect output when the lb input is low , the sd output is high. when the lb input is high the function of this pin depends upon the mode selected by the por tsel pin. fiber mode: when the fiber mode is selected, a high level at the sd output indicates a positive dif fer- ential voltage is applied to the sdh/sdl input pair . a low level at the sd output indicates a negative dif ferential voltage is applied to the sdh/sdl input pair . twisted pair mode: when the t wisted pair mode is selected, a high logic state, on the sd output indicates the presence of a received t wisted pair data signal with an amplitude exceeding a preset squelch threshold. 51 52 53 54 55 rdata0 rdata1 rdata2 rdata3 rdata4 o ttl receive data bus outputs these outputs deliver recovered receive data to the elm. the data appearing at each output may change at a 25 mbps rate. rda ta4 is received from the media first. 56 rsclk o ttl recovered symbol clock output this clock signal is used to latch data received on rda tax and to operate the elasticity buffer . the frequency of this signal is nominally 25 mhz. 57 fo i ttl transmit output disable input when the fo input is low the transmitter dif ferential outputs, tdh and tdl are disabled. 58 lb i ttl loopback enable when low, this input enables transmitterreceiver loopback capability, which causes data appearing at the transmit data bus inputs (tdatax) to be fed to the receive data bus outputs (rdat ax) and the signal detect output (sd) to be forced high. while in the loopback mode, the elm interface will not receive any data from the rdl and rdh inputs, however, the fo input must be forced low to prevent transmit data from appearing on the tdl and tdh outputs. 59 60 61 62 63 tdata4 tdata3 tdata2 tdata1 tdata0 i ttl transmit data bus inputs these inputs accept data from the elm which is to be transmitted to the attached media. the data appearing at each input may change at a 25 mbps rate. tda ta4 is transmitted on the media first.
MC68835 7 motorola timing solutions br1333 e rev 4 table 4. clock pins pin no. pin name pin type pin description 31 mclkin i ttl master clock input in amaster clock modeo users should connect an external 25mhz reference clock to this input. in aslave clock modeo users should connect this input to ground. 36 symclk o ttl symbol clock output this 25mhz output is used only in fddi master clock mode applications. in master clock mode this output is connected to the tclkin input and the symclk input of all other fddi devices in the system. in slave clock mode this output is unused and should be left unconnected. 37 bytclk o ttl byte clock output this 12.5mhz output is used only in fddi master clock mode applications. in master clock mode this output is connected to the bytclk input of all other fddi devices in the system. in slave clock mode this output is unused and should be left unconnected. 46 tclkin i ttl transmit clock input users must connect a 25mhz reference clock to this input. table 5. external component connection pins pin no. pin name pin type pin description 8 rreftpt x twisted pair t ransmitter external reference resistor connection pin an external precision resistor must be connected between this pin and ground to set the transmit output current amplitude. t o meet the transmit signal levels specified by the ansi x3t9.5 tppmd specification, rreftpt should be set to 2k w 1%. this value of rreftpt yields an output current of 40ma. for 100 ohm characteristic impedance utp applications, this current results in a 1.0v peak differential output voltage. 20 21 c1 c2 x t wisted pair adaptive equalizer feedback capacitor connection pins the external capacitor connected to these pins controls the time constant of the adaptive receive equalizer . the recommended value is 400pf . 25 tprecb x twisted pair receiver bias resistor connection pin the external precision resistor connected to this pin and ground establishes an internal reference current.this resistor should be set to a value of 3k w 1%.
MC68835 8 motorola timing solutions br1333 e rev 4 table 6. power pins pin no. pin name pin type pin description 3 vddio p cmos i/o power 47 gndio g cmos i/o ground 6 vdddig p digital logic power 40 gnddig g digital logic ground 7 gndbg g band gap regulator ground 10 vddtpt p tp transmit power 9 gndtpt g tp transmit ground 14 vddfout p fiber output power 13 gndfout g fiber output ground 24 vddtpr p tp receiver power 19 gndtpr g tp receiver ground 30 vddfin p fiber input power 27 gndfin g fiber input ground 45 vddfm p frequency multiplier power 43 gndfm g frequency multiplier ground 38 vddclk p clock power 35 gndclk g clock ground 1 2 16 17 18 32 33 34 41 48 49 50 64 gnd g substrate grounds table 7. no connect pins pin no. pin name pin type pin description 24 44 nc no connect the no connect pins must be left disconnected.
MC68835 9 motorola timing solutions br1333 e rev 4 operation of circuit blocks (see figure 3) twisted pair transmitter output and receiver input output when the twistedpair transmitter is selected by the portsel input, it is used to transmit ml t3 coded signals to the twistedpair transmit transformer as shown in figure 1. since t ransmi t w aveshapin g i s e mployed , a n e xternal transmit filter may not be required. (mlt3 is a coding scheme in which every logical high bit on the transmitter input stream produces alternately a positive or a negative pulse on the output and every logical low bit produces no positive nor negative pulse on the output.) input when t h e t wistedpai r r eceive r i s s electe d b y t he portsel input, it is used to receive ml t3 coded signals from the twistedpair receive transformer as shown in figure 1. a squelch function is applied to determine if sufficient energy exists on the media to effect data recovery. if enough energy is detected, an equalizer filters the receive signal to undo the effects of the media including attenuation, phase distortion and base line wander . the receiver inputs must be driven dif ferentially in order to assure proper operation. fiber transmitter output and receiver input output when the fiber transmitter is selected by the por tsel input, it is used to transmit nrzi coded signals to the fiber interface components as shown in figure 2. normal ecl termination techniques (with provisions for the positive logic input levels) should be used to interface the outputs with optical transceiver modules. (nrzi is a method of encoding a clock signal into a data stream. it operates by inverting the polarity of the output signal on every logical high bit and not inverting the output on every logical low bit. hence, every high bit produces a state transition on the output, while every low bit produces no s uc h t ransition. n rzi , a lon g w it h 4 b/5 b e ncoding, assures the receiving pll of a certain minimum density of clock transitions for any given data pattern.) input when the fiber receiver is selected by the por tsel input, it is used to receive dif ferential, pseudoecl, nrzi coded signals from the fiber interface components as shown in figure 2. n orma l e c l t erminatio n t echnique s ( with provisions for the positive logic input levels) should be used to interface the receive inputs of the optical transceiver modules. the fiber inputs must be driven dif ferentially in order to assure proper operation. elm interface the elm interface is a ttllevel interface composed of five parts: receive data, receive signal detect, transmit data, and two control signals, fo and lb . the transmit and receive parts each have independent clocks. receive data a d igitalphaselockloo p i s u se d t o r ecover t he incoming nominal 125 mhz data stream from the selected serial port data. the dpll maintains frequency lock with the received data with only minimal transitions in the data stream. (the fddi stream cipher algorithm, when combined with fddi' s 4b/5b coding, can generate up to sixty bits, which is 480 ns, without a transition on the media). the recovered data and clock are used by the decoder to extract the received nrz data stream. data received is output on the rda t a4 rda ta0 outputs. five new bits are output on each rising edge of rsclk. the serial data reception order is: rda ta4, first bit received, and rda t a0, last bit received. rsclk is derived from the incoming bit stream. data on rdata4 rdata0 is not aligned to symbol boundaries. receive signal detect when the fiber port is selected via por tsel, the signal detect output, sd is simply a level translation of the sdh and sdl inputs and indicates whether the receive data, rdh and rdl, is valid. this indicates that enough light energy is being received by the fiber optic receiver . when lb is low , sd is driven high and when the a w ake input is low , the sd output is driven low . when the twistedpair port is selected via portsel, sd is derived from a combination of signals from the squelch and auto equalization functions. for sd to be asserted, the squelch must detect suf ficient energy on rdh and rdl, and the equalizer must have equalized. transmit data the 5bit data symbols to be transmitted are obtained from the elm device via the tda t a4 tda t a0 inputs. a new 5bit symbol is strobed in on each rising edge of tclkin and a r e o utpu t a t t h e t dh/ l o utput . t h e s eria l d ata transmission order is: tdat a4, first bit transmitted, tda ta0, last bit transmitted. when the fiber mode is selected via por tsel, the encoder converts the transmit data stream into nrzi and the digital serial transmit data stream is output as pseudoecl on tdh and tdl. when the twistedpair mode is selected via por tsel, the nrzi data stream is converted to ml t3 coded data and output at the tdh/tdl outputs.
MC68835 10 motorola timing solutions br1333 e rev 4 transmit disable (fo ) and parallel loopback (lb ) controls when the fo and lb inputs are high, the MC68835 is in its normal mode of operation. when fo is low , tdh and tdh are both forced low (quiet state). when the lb input is high, the MC68835 is in normal operation. when lb is low, the MC68835 is in loopback mode. in this mode, the serial transmit data stream that is normally delivered to the tdh and tdl outputs is also routed to the receive data circuit where it is recovered and delivered to the rda t a4 through rda t a0 outputs. if it is undesirable to place the serial data stream on the tdl and tdh outputs, the f o i npu t m us t b e d rive n t o t h e l o w l ogi c s tate. additionally, when the lb input is low , the rdh and rdl and sdh and sdl inputs are ignored. furthermore, the signal detect output, sd is driven high when lb is in the low logic state. frequency multiplier the frequency multiplier block utilizes the external 25 mhz signal (tclkin) as a reference to produce the 125mhz signal which is needed for operation of the digital phase locked loop (dpll) circuitry . system management the system management block controls the standby mode. electrical characteristics absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. functional operation of the device is not implied at these or any other conditions in excess of those indicated in the operation sections of this data sheet. exposure to absolute maximum ratings conditions for extended periods can adversely af fect device reliability . parameter symbol min max unit storage temperature range tstg 65 150 deg c power supply voltage range vdd 0.3 7 v v oltage on any ttl compatible input pin v 0.3 vdd+0.3 v v oltage on rdh/rdl input pins with respect to ground v 0.3 vdd+0.3 v dif ferential voltage on rdh/rdl input pins v recommended operating conditions parameter symbol min max unit power supply voltage range vdd 4.75 5.25 v ambient operating temperature range ta 0 70 deg c
MC68835 11 motorola timing solutions br1333 e rev 4 esd although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (esd) during handling and mounting. motorola employs a humanbody model (resistance = 1500 w , capacitance 100pf). the MC68835 will withstand exposure to 2kv standard human body model esd testing. ttl/cmos input and output dc characteristics (unless otherwise noted minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges) parameter symbol test conditions min typ max unit ttl compatible inputs low state ttl compatible input v oltage vil (ttl) 0.8 v high state ttl compatible input v oltage vih (ttl) 2.0 v input current ttl compatible input pins ii (ttl) 10 ua ttl/cmos compatible outputs low state ttl/cmos compatible output v oltage vol iol = 4ma 0.45 v high state ttl/cmos compatible output v oltage voh ioh = 400ua tbd v high state ttl/cmos compatible output v oltage voh ioh = 4ma 2.4 v three state output leakage current ioz 0v voz vdd 50 ua twisted pair input and output dc characteristics (unless otherwise noted minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges) parameter symbol test conditions min typ max unit twisted pair receiver inputs t wisted pair common mode input v oltage range vicmtp 4.75v vdd 5.25v 2.2 tbd v twisted pair peak differential input voltage vidtp 4.75v vdd 5.25v 1 v twisted pair differential input resistance rdifftp 4.75v vdd 5.25v 10 k w t wisted pair common mode input current iicmtp 4.75v vdd 5.25v 10 ua twisted pair dif ferential input squelch threshold voltage vitpsq 4.75v vdd 5.25v tbd tbd v
MC68835 12 motorola timing solutions br1333 e rev 4 twisted pair input and output dc characteristics (continued) (unless otherwise noted minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges) parameter symbol test conditions min typ max unit twisted pair transmitter outputs twisted pair dif ferential output current high current state iodhtp 4.75v vdd 5.25v vo = vdd 0.5v rreftpt =2k w 1% 40 ma twisted pair dif ferential output current low current state iodltp 4.75v vdd 5.25v vo = vdd 0.5v 0 0.5 tbd ma twisted pair differential output offset current iodostp 4.75v vdd 5.25v vo = vdd 0.5v 0.5 ma twisted pair dif ferential output amplitude error 4.75v vdd 5.25v vo = vdd 5 5 % twisted pair differential output voltage compliance 4.75v vdd 5.25v vo = vdd 1.1v 2 2 % 1. for a logic high, rdl must be at least v idif f(min) but no more than v idif f(max) lower than rdh. for a logic low , rdl must be at least v idiff(min) but no more than vidiff(max) higher than rdh. fiber input and output dc characteristics (unless otherwise noted minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges) parameter symbol test conditions min typ max unit fiber receiver inputs fiber differential input voltage range 1 vidiff 4.75v vdd 5.25v 0.5 1.1 v fiber common mode input voltage range 2 vicm 4.75v vdd 5.25v vdd 1.9 vdd 0.8 v fiber high state input current iih 4.75v vdd 5.25v vih = vdd0.8v 50 m a fiber low state input current iil 4.75v vdd 5.25v vil = vdd1.9v 0.5 m a fiber transmitter outputs fiber high state output voltage voh 4.75v vdd 5.25v ioh = 20ma vdd 1.1 vdd 0.8 v fiber low state output voltage vol 4.75v vdd 5.25v iol = 20ma vdd 1.8 vdd 1.6 v 1. for a logic high, rdl must be at least v idif f(min) but no more than v idif f(max) lower than rdh. for a logic low , rdl must be at least v idiff(min) but no more than vidiff(max) higher than rdh. 2. this is the range of valid signal voltages that may be applied to the rdl and rdh inputs for proper operation in fiber mode.
MC68835 13 motorola timing solutions br1333 e rev 4 power supply dc characteristics parameter symbol test conditions min typ max unit power supply current idd vdd = 5.25v 1 300 ma power supply current standby mode (a wake input low) iddsb vdd = 5.25v tbd ua 1. the supply current consumption depends upon the mode of operation selected. tclkin timing (see figure 5) parameter symbol test conditions min typ max unit tclkin period (1) tck1 40 ns tclkin time low tck2 8 ns tclkin time high tck3 8 ns tclkin transition time tck4 5 ns figure 5. tclkin input voltage levels for timing measurements tck4 0.8v 2v tck1 tck2 tck3 3v 0v tclkin tp transmit switching characteristics (see figure 7) parameter symbol test conditions min typ max unit twisted pair differential output transition time zero to positive ttpt1 4.75v vdd 5.25v 1 4 ns twisted pair differential output transition time zero to negative ttpt2 4.75v vdd 5.25v 1 4 ns twisted pair differential output transition time positive to zero ttpt3 4.75v vdd 5.25v 1 4 ns twisted pair differential output transition time negative to zero ttpt4 4.75v vdd 5.25v 1 4 ns twisted pair differential output jitter ttpt5 4.75v vdd 5.25v 1,2 0.8 ns 1. measured dif ferentially across the output of test load a 2. specification established by design and laboratory characterization
MC68835 14 motorola timing solutions br1333 e rev 4 figure 6. tp tramitter test load 50 w 50 w +5v to tp transmitter outputs figure 7. tdh/l differential twisted pair transmit output timing characteristics (note: specification established by design and laboratory characterization) tdh/l (differential) ttpt1 10% 90% ttpt2 ttpt3 90% ttpt4 10% ttpt5 0.5v tp transmit switching characteristics (see figure 9) parameter symbol test conditions min typ max unit fiber differential output transition time low to high tft1 4.75v vdd 5.25v 0.9 3 ns fiber differential output transition time high to low tft2 4.75v vdd 5.25v 0.9 3 ns fiber differential output jitter tft3 4.75v vdd 5.25v 1 750 ps 1. specification established by design and laboratory characterization figure 8. fiber differntial driver test load 50 w 3v to fiber (ecl) output pins 50 w 0.1 m f
MC68835 15 motorola timing solutions br1333 e rev 4 figure 9. fiber transmit driver output timings tft1 3.3v 4v tdh/l (differential) tft2 tft3 parallel interface timing (see figure 11) parameter symbol test conditions min typ max unit rsclk period tpi1 36 40 44 ns rsclk time low tpi2 1 18 22 ns rsclk time high tpi3 1 18 22 ns time to rdata invalid tpi4 8 ns time to rdata valid tpi5 32 ns tclkin period tpi6 39 41 ns tclkin time low tpi7 18 22 ns tclkin time high tpi8 18 22 ns tdata setup time tpi10 2 12 40 ns tdata hold time tpi11 2 0 28 ns 1. this parameter is specified with the receiver operating at 125 mhz. 2. this is with respect to tclkin
MC68835 16 motorola timing solutions br1333 e rev 4 figure 10. ttl compatible output ac test load 1k w +5v to ttl compatible output pins 15pf figure 11. parallel interface timing rsclk rdata[4:0] tclkin tdata[4:0] tpi4 tpi5 tpi3 tpi2 tpi1 1.6v 1.5v 2.0v valid valid valid 2.0v 0.4v tpi8 tpi7 tpi6 1.6v tpi10 tpi11 2.0v 0.4v
MC68835 17 motorola timing solutions br1333 e rev 4 outline dimensions fa suffix plastic tqfp package case 93102 issue d e c h k r 0.08 (0.003) 0.25 gauge plane detail l ???? ???? ???? ???? ???? ???? a 1 17 16 48 33 32 64 49 m m b v ref 2x u g 15x 4pl detail l -t- seating plane j f d n section m-m t 0.08 (0.003) m notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrustion. allowable protrustion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined where the bottom of the lead exits the plastic. 4. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.35 (0.014). dambar can not be located on the lower radius of the foot. minimum space between protrusion and an adjacent lead is 0.07 (0.003). 5. as plated solder thickness shall be 0.0076 (0.0003) / 0.0203 (0.008). dim a min max min max inches 9.90 10.10 0.390 0.398 millimeters b 9.90 10.10 0.390 0.398 c 2.45 0.096 d 0.17 0.27 0.007 0.011 e 1.80 2.20 0.071 0.087 f 0.17 0.24 0.007 0.009 g 0.50 bsc 0.020 bsc h 0.35 0.014 j 0.09 0.20 0.004 0.008 k 0.45 0.75 0.018 0.030 n 0.09 0.16 0.004 0.006 p 1.20 1.30 0.047 0.051 r 0 9 0 9 s 12.00 ref 0.472 ref u 0.95 1.05 0.037 0.041 v 12.00 ref 0.472 ref y 0.95 1.05 0.037 0.041 base metal s ref 2x y 4x p
MC68835 18 motorola timing solutions br1333 e rev 4 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . literature distribution centers: usa & europe: motorola literature distribution; p .o. box 20912; phoenix, arizona 85036. jap an: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, t okyo 141 japan. asia-p acific: motorola semiconductors h.k. ltd.; silicon harbour center , no. 2 dai king street, t ai po industrial estate, tai po, n.t., hong kong. MC68835/d ? codeline to be placed here

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